A. Field of the Invention
The invention relates to testing analog circuit modules and in particular analog circuit modules on a carrier or printed circuit board.
B. Related Art
The invention is an improvement on U.S. Pat. No. 5,107,208, which is incorporated herein by reference. This prior art scheme is particularly suited to dividing integrated circuits into submodules for testing.
The invention is also related to the field of boundary scan of digital circuits. A general scheme for testing digital circuits on a carrier has been proposed in IEEE Std 1149.1-1990, "IEEE Standard Test Access Port and Boundary-Scan Architecture". This scheme allows digital circuits to be designed for testability.
Another digital testing scheme, which uses a divide and conquer approach, is found in E. J. McCluskey and S. Boaorgui-Nesbat, "Design for Autonomous Test", IEEE Transactions on Computers, Vol. C-30, No. 11, pp. 886-875, 11/81.
Analog circuits also need to be designed for testability. The typical analog circuit is more difficult to test than the typical digital circuit, for reasons including the following. Analog modules are tightly coupled, with everything depending on everything else. Design margins are tight for analog circuits, as compared with large safety margins built into digital circuits. Analog circuits have complex signal types, which mean that direct access is usually required in order to observe or control analog signals, unlike digital signals which can be easily observed/controlled using shift registers. There is no ability to freeze internal states, such as charge on capacitors, of analog circuits, while the digital circuits have enable signals or clocks. Analog circuits are sensitive to input noise and output loading effects. Analog circuits do not have well-defined I/O port types. A single port may serve multiple purposes, such as charging/discharging of a capacitor, plus detection of threshold voltages, so that classification into either "input" or "output" may be obscured. There is no formal specification for analog functions, unlike the simple boolean equations or hardware description languages used in the digital world. There are no elementary and universal fault models for marginal failures in analog circuits, unlike the "stuck-at-0/1" models which were highly successful in digital circuits, but are not sufficient in the analog world.
Some design for testability schemes for analog/mixed signal circuits have been presented. These include
K. D. Wagner and T. W. Williams, "Design for Testability of Mixed Signal Integrated Circuits", Proceedings of the IEEE 1988 International Test Conference, paper 39.1, pp. 823-828, 1988; PA1 P. Fasang et al., "Design for Testability for Mixed Analog/Digital ASICs", Proceedings of the IEEE 1988 Custom Integrated Circuits Conference, pp. 16.5.1-16.5.4, 1988; PA1 U.S. Pat. No. 4,918,379; PA1 S. Freeman "Testing large Analog/Digital Signal Processing Chips, IEEE Transactions on Consumer Electronics, Vol. 36, No. 4, pp. 813-818, November 1990; PA1 F. Goodenough, "Build Mixed-Signal ASICS without Analog Cells", Electronic Design, pp. 163-165, Sep. 12, 1991; PA1 M. Soma etc., "Panel: P1149.4 Mixed-Signal Test Bus Framework Proposal", International Test Conference 1992 Proceedings, Paper 29.1-29.3, September 1992. PA1 They are not hierarchical, i.e. they do not apply uniformly to both chip and board levels. PA1 Continuity of normal signal path between submodules (whether at chip or board level) is not ensured. This implies that after the completion of individual testing for submodules, additional testing at the next higher level is still necessary to ensure the proper connection between submodules. PA1 Applicability of each scheme is often restricted to a specific topology or a specific class of analog circuits. For example, a popular misrepresentation of analog circuits consists of a linear chain of analog blocks, each having exactly one input and one output. This misrepresentation leads to testing schemes which lack general applicability. PA1 True Analog AC testing is often avoided or deferred. Some typical approaches are:
These schemes suffer from some or all of the following drawbacks.
Isolate the analog portion from a mostly-digital circuit, such that analog testing can be dealt with later by someone else. This approach does not work for mostly-analog circuits, or cases when the analog testing is too complex; PA2 Convert the input/output ports of an analog block to digital (using D/A and A/D converters) so that the testing can be conducted digitally. Only DC (static) testing for the analog block can be done in this case, while real time AC (dynamic) testing is not feasible. Large area overhead is also incurred by the converters necessary for every analog I/O port.